`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/09/12 11:09:03
// Design Name:
// Module Name: adc_interface
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module adc_interface (
	input adc_clk,
	input  [ 7:0] ADC_DI_P ,
	input  [ 7:0] ADC_DI_N ,
	output [15:0] adc_data
);


	wire [7:0] adc_ds_data;

	genvar i;

	generate
		for (i=0; i < 8; i=i+1) begin: inst_adc_data

			IBUFDS #(
				.DIFF_TERM   ("TRUE"   ), // Differential Termination
				.IBUF_LOW_PWR("TRUE"   ), // Low power="TRUE", Highest performance="FALSE"
				.IOSTANDARD  ("LVDS_25")  // Specify the input I/O standard
			) IBUFDS_inst (
				.O (adc_ds_data[i]  ), // Buffer output
				.I (ADC_DI_P[i]), // Diff_p buffer input (connect directly to top-level port)
				.IB(ADC_DI_N[i])  // Diff_n buffer input (connect directly to top-level port)
			);

			IDDR #(
				.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
				//    or "SAME_EDGE_PIPELINED"
				.INIT_Q1     (1'b0           ), // Initial value of Q1: 1'b0 or 1'b1
				.INIT_Q2     (1'b0           ), // Initial value of Q2: 1'b0 or 1'b1
				.SRTYPE      ("SYNC"         )  // Set/Reset type: "SYNC" or "ASYNC"
			) IDDR_inst (
				.Q1(adc_data[(i*2)+1]), // 1-bit output for positive edge of clock
				.Q2(adc_data[i*2]    ), // 1-bit output for negative edge of clock
				.C (adc_clk          ), // 1-bit clock input
				.CE(1'b1             ), // 1-bit clock enable input
				.D (adc_ds_data[i]   ), // 1-bit DDR data input
				.R (1'b0             ), // 1-bit reset
				.S (1'b0             )  // 1-bit set
			);

		end


	endgenerate



endmodule
